1. Field of the Invention
The present invention relates to a MIS (i.e., Metal Insulator Semiconductor) type semiconductor device and a method for manufacturing the same, and more particularly to a horizontal type DMISFET (i.e., Double-diffused MIS Field Effect Transistor) and a method for manufacturing the same.
2. Description of the Related Art
Heretofore, DMOSFETs (i.e., Double-diffused Metal Oxide Semiconductor Field Effect Transistors) have been known as semiconductor power devices for controlling both a relatively large current and a relatively large voltage. Of these DMOSFETs, a horizontal type DMOSFET has its drain electrode disposed in its surface. According to principles of the FET, the horizontal type DMOSFET uses either electrons or electric holes as its majority carriers in operation, and is therefore free from any stored carrier effect. Due to this freedom, the horizontal type DMOSFET is excellent in switching characteristic and in punch-through resistance. Consequently, the horizontal type DMOSFET has widely been used in inductive loads, for example such as switching regulators and the like instruments.
FIG. 15 shows a plan view of a conventional horizontal MIS type semiconductor device. FIG. 16 shows a cross-sectional view of the conventional horizontal MIS type semiconductor device shown in FIG. 15. Incidentally, the cross-sectional view shown in FIG. 16 is taken along a center line L through which a center of a drain region is connected with a center of a base region in the conventional MIS type semiconductor device. Hereinbelow, the conventional horizontal MIS type semiconductor device will be described.
As shown in FIG. 16, the conventional horizontal MIS type semiconductor device, more particularly, conventional DMOSFET uses a P+-type silicon substrate 51 in which a Pxe2x88x92-type region 52 for example is previously formed by a suitable crystal growth process such as epitaxial growth processes. Selectively formed in this Pxe2x88x92-type region 52 is an N-type well region 53. Selectively formed in a major surface of the thus formed N-type well region 53 is a first P-type base region 54. Selectively formed in this first P-type base region 54 is a P+-type base region 55. On the other hand, selectively formed in the N-type well region 53 is an N+-type drain region 56. Further, selectively formed in the first P-type base region 54 is an annular P+-type source region 57 which is disposed adjacent to a peripheral portion of the P+-type base region 55. This annular P+-type source region 57 is oppositely disposed from the N+-type drain region 56. A gate electrode 59 is formed on a gate oxide (i.e., insulation) film 58 which is formed between the annular P+-type source region 57 and the N+-type drain region 56. Incidentally, in FIG. 15, the reference numeral 60 denotes an element isolation insulation film.
A first interlayer insulation film 61 is formed to cover the entire surface of the semiconductor device including the gate electrode 56. As is clear from FIG. 16, a first contact window 62 is formed on the N+-type drain region 56 of this first interlayer insulation film 61. Through the first contact window 62, a first layer drain electrode 63 extends upward. On the other hand, a second contact window 64 is formed on both the P+-type base region 55 and the annular P+-type source region 57. Through the second contact window 64, a source electrode 65 extends upward, as shown in FIG. 16. A second interlayer insulation film 66 is formed to cover the entire surface of the semiconductor device including both the first layer drain electrode 63 and the source electrode 65. A third contact window 67 is formed on the first layer drain electrode 63 in the second interlayer insulation film 66. Through the third contact window 67, a second layer drain electrode 68 extends upward. The first layer drain electrode 63 is combined with the second layer drain electrode 68 to form a drain electrode assembly. The thus formed semiconductor device has its surface covered with a cover insulation film 69. In this conventional horizontal MIS type semiconductor device, as is clear from FIG. 15, the first P-type base region 54 assumes an octagonal-shaped configuration in plan view to improve the semiconductor device in integration density (i.e., cell density per unit area).
However, the conventional horizontal type DMOSFET has the disadvantage that: when an over-voltage such as surge voltages and counter electromotive forces caused when the DMOSFET connected with an inductive load is turned off is applied to a drain electrode of the DMOSFET, both the displacement current and the breakdown current are forced to flow, so that the DMOSFET is impaired in its endurance of high potential (i.e., over-voltage) failure. In other words, the displacement current concentrates in an area situated on a center line L (shown in FIG. 15) along which is defined the shortest distance between the N+-type drain region 56 and the annular P+-type source region 57 which is oppositely disposed from the N+-type drain region 56. Concentration of the displacement current in the above area is due to the fact that the area in the above-mentioned shortest distance is lowest in resistance to the displacement current. On the other hand, the breakdown current concentrates in each of the corner portions of the polygonal-shaped first P-type base region 54 since the electric field strength is large in each of these corner portions of the first base region 54.
When both the displacement current and the breakdown current flow in a manner described above, a PN junction formed between the base and the emitter (i.e., between the first base region 54 and the annular P+-type source region 57) of a parasitic NPN transistor (which is constructed of: the N-type well region 53 serving as a collector; the P-type first base region 54 serving as a base; and, the annular P+-type source region 57 serving as an emitter) is forward-biased, which facilitates the turn-on action of the above-mentioned parasitic NPN transistor. As a result, current concentration is induced, which leads to a high potential failure of the conventional horizontal type DMOSFET. Due to this, the conventional horizontal type DMOSFET is poor in its endurance of high potential failure.
Another conventional horizontal type DMOSFET improved in its endurance of an over-voltage applied to its drain electrode is disclosed, for example, in Japanese Patent Laid-Open No. Hei9-139438 in which: a deep P-type base region is formed in a first P-type base region in a manner such that the deep P-type base region is larger in depth than the first P-type base portion to decrease in base resistance a parasitic NPN transistor of the DMOSFET, which makes it hard to turn on the parasitic NPN transistor so that an object of the conventional DMOSFET disclosed in the Japanese Patent Laid-Open No. Hei9-139438 is accomplished.
Another conventional but vertical type DMOSFET improved in its endurance of an over-voltage applied to its drain electrode is disclosed, for example, in Japanese Patent Laid-Open No. Hei6-97448 in which: a corner portion of a P-type base region is made free from any formation of an N+-type source region; and, an hFE (i.e., common-emitter static forward current transfer ratio) in the corner portion of the P-type base region is lowered together with the base resistance of a parasitic NPN transistor of the DMOSFET to make it hard to turn on this parasitic NPN transistor.
However, the conventional horizontal type DMOSFET disclosed in the Japanese Patent Laid-Open No. Hei9-139438 has the disadvantage that: since the deep P-type base region is made deeper in depth than the first base region in order to lower the base resistance of the parasitic NPN transistor, the conventional horizontal type DMOSFET increases in the number of process steps in manufacturing thereof, and is hard to fabricate due to its delicate region structures, which makes it hard to improve the conventional horizontal type DMOSFET in integration density.
On the other hand, although the other conventional but vertical type DMOSFET disclosed in the Japanese Patent Laid-Open No. Hei6-97448 is effective against the breakdown current, it has the disadvantage that: since no consideration is given to the displacement current, concentration of the displacement current occurs.
In view of the above, it is an object of the present invention to provide a MIS (i.e., Metal Insulator Semiconductor) type semiconductor device and a method for manufacturing the same, and more particularly to a horizontal type DMISFET (i.e., Double-diffused MIS Field Effect Transistor) and a method for manufacturing the same, wherein the horizontal type DMISFET of the present invention is improved in its endurance of an over-voltage applied to its drain electrode.
According to a first aspect of the present invention, there is provided a MIS type semiconductor device comprising:
a semiconductor substrate;
a high concentration drain region of a first conductive type selectively formed in a major surface of the semiconductor substrate;
a first base region of a second conductive type selectively formed in the major surface of the semiconductor substrate so as to be separated from the high concentration drain region;
a source region of the first conductive type formed in the first base region of the second conductive type; and
an insulated-type gate electrode formed between the source region of the first conductive type and the high concentration drain region of the first conductive type;
wherein the source region of the first conductive type is not disposed on a center line through which, in plan view, a center of the high concentration drain region of the first conductive type is connected with a center of the base region of the second conductive type.
In the foregoing, a preferable mode is one wherein:
a high concentration base region of the second conductive type is selectively formed in the first base region of the second conductive type; and
the source region of the first conductive type is disposed adjacent to a peripheral portion the high concentration base region of the second conductive type.
Also, a preferable mode is one wherein:
the first base region of the second conductive type has its outline formed into a polygonal-shaped configuration in plan view;
the source region of the first conductive type has its source portions not disposed on the center line, the source portions corresponding to corner portions of the polygonal-shaped configuration;
Also, a preferable mode is one wherein:
the first base region of the second conductive type assumes a polygonal-shaped configuration in plan view; and
the source region of the first conductive type is not disposed in any corner portions of the polygonal-shaped configuration.
Furthermore, a preferable mode is one wherein: a plurality of the source regions each of the first conductive type and a plurality of the high concentration drain regions each of the first conductive type are provided.
According to a second aspect of the present invention, there is provided a method for manufacturing a MIS type semiconductor device comprising: a semiconductor substrate; a high concentration drain region of a first conductive type selectively formed in a major surface of the semiconductor substrate; a first base region of a second conductive type selectively formed in the major surface of the semiconductor substrate so as to be separated from the high concentration drain region; a source region of the first conductive type formed in the first base region of the second conductive type; and, an insulated-type gate electrode formed between the source region of the first conductive type and the high concentration drain region of the first conductive type; the method comprising the step of:
selectively forming the first base region of the second conductive type in the main surface of the semiconductor substrate;
selectively forming the high concentration base region of the second conductive type in the first base region of the second conductive type;
selectively forming the high concentration drain region of the first conductive type in the semiconductor substrate; and
selectively forming the source region of the first conductive type in the first base region of the second conductive type so as to be disposed adjacent to a peripheral portion of the high concentration base region of the second conductive type but not disposed on a center line through which, in plan view, a center of the high concentration drain region of the first conductive type is connected with a center of the base region of the second conductive type.
In the foregoing, a preferable mode is one wherein: the step of selectively forming the high concentration drain region of the first conductive type and the step of selectively forming the first base region of the second conductive type are simultaneously performed.
As described above, in the MIS type semiconductor device of the present invention and the method of the present invention for manufacturing the semiconductor device each having the above construction, since the source region of the first conductive type is formed in configuration in plan view so as to be not disposed on the center line through which the center of the drain region of the first conductive type is connected with the center of the first base region of the second conductive type, it is possible for the semiconductor device of the present invention to suppress any concentration of both the displacement current and the breakdown current therein, which makes it hard to turn on the parasitic NPN transistors.
Consequently, the horizontal type DMISFET of the present invention having the above construction is remarkably improved in its endurance of an over-voltage applied to the drain electrode thereof.